1. Field of the Invention
The present invention relates to a pressure-connection type semiconductor device and a method of fabricating the same, and more particularly, it relates to a pressure-connection type semiconductor device in which a thermal compensator and a semiconductor base substrate are in contact with each other in an alloy-free state, and a method of fabricating the same.
2. Background of the Invention
In a well-known type of conventional pressure-connection type semiconductor device, a semiconductor base substrate is incorporated in the device in an alloy-free state, i.e., with no blazing.
FIG. 9 is a sectional view showing a power gate turnoff thyristor (hereinafter referred to as "GTO") which is formed as a conventional alloy-free pressure-connection type semiconductor device. In the pressure-connection type semiconductor device shown in FIG. 9, a cathode layer 2K, an anode layer 2A and a gate electrode layer 2G are formed on upper and lower surfaces and a central portion of the upper major surface of a semiconductor substrate 1 respectively, thereby defining a semiconductor base substrate 100.
Further, first and second discoidal thermal compensators 3 and 6 are provided in contact with surfaces of the anode and cathode layers 2A and 2K respectively, while anode and cathode copper blocks 7 and 8 are provided to be in contact with surfaces of the first and second thermal compensators 3 and 6 in an alloy-free state respectively.
This substrate is stored in a cylindrical ceramic casing 9, so that base portions of the anode and cathode copper blocks 7 and 8 are coupled to the casing 9 through metal flanges 10a and 10b respectively.
A through hole 6H is provided in a central portion of the second thermal compensator 6 provided on the gate electrode layer 2G while a non-through hole 8H is provided in the cathode copper block 8 in correspondence thereto, so that a gate electrode holder 11 is slidably inserted in an insertion hole which is defined by the through hole 6H and the non-through hole 8H. A gate electrode 12 is connected to an end of an L-shaped lead wire 10 which is drawn out toward the exterior of the casing 9.
FIG. 10 is an enlarged view showing a portion around the semiconductor base substrate 100. Referring to FIG. 10, polyimide varnish 1a is applied to an outer peripheral edge of the semiconductor substrate 1, in order to insulate and protect a p-n junction part which is exposed on this outer peripheral edge. An insulating/holding material 4 is formed on the semiconductor substrate 1 to cover surfaces of the polyimide varnish 1a and the overall step portion of the first thermal compensator 3 for preventing creeping discharge along the outer peripheral edge of the semiconductor substrate 1 and protecting the same, and fixed to the first thermal compensator 3. The insulating/holding material 4 is formed by applying viscose liquid resin onto the surfaces of the polyimide varnish 12a and the overall step portion of the first thermal compensator 3 while placing the semiconductor base substrate 100 on the first thermal compensator 3, and hardening the resin. This insulating/holding material 4 adheres to the first thermal compensator 3, thereby preventing misregistration of the semiconductor base substrate 100 and the first thermal compensator 3.
In employment in a prescribed apparatus, the pressure-connection type semiconductor device is inserted between an anode member 20A and a cathode member 20K which are provided on the prescribed apparatus as shown in FIG. 9. The anode and cathode members 20A and 20K are urged by external springs (not shown) along arrows respectively, so that the lower surface of the cathode member 20K is in pressure contact with the upper surface of the cathode copper block 8 while the upper surface of the anode member 20A is in pressure contact with the lower surface of the anode copper block 7. Thus, the cathode member 20K is reliably electrically connected with the cathode layer 2K through the cathode copper block 8 and the thermal compensator 6.
In the conventional pressure-connection type semiconductor device having the aforementioned structure, the viscose liquid resin which is applied to the surfaces of the polyimide varnish 1a covering the outer peripheral edge of the semiconductor base substrate 100 and the overall step portion of the first thermal compensator 3 for forming the insulating/holding material 4 may penetrate into a clearance between the semiconductor base substrate 100 and the first thermal compensator 3 by a capillary phenomenon. In a state illustrated in FIG. 11, which is a partially enlarged view showing the outer peripheral edge of the semiconductor base substrate 100, the insulating/holding material 4 penetrates into a clearance between the cathode layer 2A provided on the lower major surface of the semiconductor base substrate 100 and the first thermal compensator 3, to form a flash 4a.
In such a state, electrical contact between the semiconductor base substrate 100 and the first thermal compensator 3 is rendered so imperfect that electric characteristics are deteriorated in a short time or local stress is concentrated on the semiconductor base substrate 100 when force is applied from the exterior for pressure connection, and hence the semiconductor base substrate 100 itself may be broken as the case may be, leading to yield reduction in fabrication of the device.